Several clock pulse regenerators have been proposed which produce, in response to an incoming digital data signal a sequence of clock pulses substantially free from phase jitter. The digital data is, for example, an NRZ (nonreturn to zero) signal. One conventional clock pulse regenerator limits the regenerated clock pulses with a high Q filter to suppress phase jitter. This approach, however, encounters a problem in that the resultant clock pulses are undesirably phase-shifted so that an additional delay circuit is required for compensation for the phase shift. Additionally, inasmuch as this approach is of the analog type, it is unsuitable for large scale integration techniques. Furthermore, a considerable amount of time is required for the regenerated clock pulse to be initially synchronized with the incoming digital data, and the resultant clock pulse is liable to vary in phase with ambient temperature variation.
Another conventional clock regenerator comprises a voltage controlled oscillator for producing output pulses of a repetition period approximately equal to the clock period of a digital input signal, a phase detector for phase-detecting the input signal with reference to the output pulses to produce a detection output of a voltage dependent on the phase difference between the repetition and clock period, and a negative feedback loop for controlling the oscillator in response to the detection output. The regenerator is capable of readily phase-synchronizing the output pulses with the clock periods and of achieving a high effective Q value by adjusting the loop gain to thereby appreciably raise the stability of clock regeneration against noise, jitter and the like. The oscillator, however, follows the clock period with a considerable delay at the beginning either when the channel of the input modulated signal is switched to another channel or when the modulated signal is supplied to the receiver in bursts.
Other related prior art circuits are disclosed in, for example, U.S. Pat. Nos. 4,064,361 and 4,087,627.